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[Other resourceVHDL_2Ddwt_ALL

Description: 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸
Platform: | Size: 1467455 | Author: chiahao | Hits:

[WaveletDwt离散db小波

Description: 小波变换子程序-Wavelet Transform Subroutine
Platform: | Size: 4096 | Author: | Hits:

[Graph programwlift_bior_7_9_JPEG2000

Description: jpeg2000中的空间变换中的DWT,9/7有损小波正变换,这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 wavelet is detrimental to transform, which is in the ADI blackfin535 DSP platform
Platform: | Size: 44032 | Author: chenlei | Hits:

[Graph programwlift_inv_bior3_5_JPEG2000

Description: jpeg2000中的空间变换中的DWT,5/3无损小波逆变换,这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 5/3 non-destructive inverse wavelet transform, which is in the ADI blackfin535 DSP platform
Platform: | Size: 41984 | Author: chenlei | Hits:

[Graph programwlift_inv_bior7_9_JPEG2000

Description: jpeg2000中的空间变换中的DWT,9/7有损小波逆变换,这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 inverse wavelet transform detrimental, which is in the ADI blackfin535 DSP platform
Platform: | Size: 43008 | Author: chenlei | Hits:

[VHDL-FPGA-VerilogVerilogHDL

Description: 人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习-Posts
Platform: | Size: 1871872 | Author: heilongjiang | Hits:

[VHDL-FPGA-VerilogVHDL_2Ddwt_ALL

Description: 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸-This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission
Platform: | Size: 1467392 | Author: chiahao | Hits:

[Other Embeded programwavelet_lifting_pld

Description: 小波提升Verilog代码,运行于quartusⅡ开发环境。-Wavelet Lifting Verilog code, running on the quartus Ⅱ development environment.
Platform: | Size: 495616 | Author: chalin tong | Hits:

[Compress-Decompress algrithmsdwt(SPIHT256)

Description: 可用的基于小波的spiht算法,可以自己设定小波分解基数,做成人机交互界面,直观-Available to the SPIHT algorithm based on wavelet, wavelet decomposition can be set for the base, resulting in human-computer interaction interface, intuitive
Platform: | Size: 4057088 | Author: 李雨 | Hits:

[VHDL-FPGA-Verilogverilog

Description: Verilog jpec coder encoder source code
Platform: | Size: 283648 | Author: Martin | Hits:

[WaveletDWT

Description: It s implementation on DWT. This was wrttend in verilog.
Platform: | Size: 3072 | Author: vasantha Kumar | Hits:

[Compress-Decompress algrithmsDWT

Description: deals with implementation of DWT
Platform: | Size: 612352 | Author: ibbu | Hits:

[VHDL-FPGA-Verilogdwt2d_latest[1].tar

Description: 小波变换的开源代码(Verilog HDL)包括有测试文件,本人看过,挺好。-code of dwt
Platform: | Size: 413696 | Author: 陈先生 | Hits:

[VHDL-FPGA-Verilogcodes

Description: VERILOG CODE FOR DWT IMAGE COMPRESSION
Platform: | Size: 16384 | Author: vijayaragavan | Hits:

[VHDL-FPGA-Verilogdwt

Description: 基于 verilog的卷积运算代码,应用于离散小波分析。-verilog conv
Platform: | Size: 1024 | Author: 方宁略 | Hits:

[WaveletDWT_xilinx

Description: Dwt(Discrete wavelet transform). verilog code
Platform: | Size: 583680 | Author: Bahu | Hits:

[Graph programDWT_verilog-code

Description: 图像压缩是图像处理中的一个重要课题,在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中,我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个,从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz,功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
Platform: | Size: 1473536 | Author: asde198250 | Hits:

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